The present invention relates to the manufacturing of semiconductor devices, and more particularly, to utilization of copper and copper alloy metallization in low-k semiconductor devices.
The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing sub-micron-sized, low resistance-capacitance (RC) metallization patterns. This is particularly applicable when the sub-micron features, such as vias, contact areas, lines, trenches, and other shaped openings or recesses have high aspect ratios (depth-to-width) due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, usually of doped monocrystalline silicon (Si), electrically isolated transistors, and other structures, and a plurality of sequentially formed inter-metal dielectric layers and electrically conductive patterns. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by inter-wiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns of vertically spaced metallization levels are electrically interconnected by vertically oriented conductive plugs filling via holes formed in the inter-metal dielectric layer separating the metallization levels, while other conductive plugs filling contact holes establish electrical contact with active device regions, such as a source/drain region of a transistor, formed in or on a semiconductor substrate. Conductive lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise five or more levels of metallization to satisfy device geometry and microminiaturization requirements.
A commonly employed method for forming conductive plugs for electrically interconnecting vertically spaced metallization levels is known as xe2x80x9cdamascenexe2x80x9d -type processing. Generally, this process involves forming a via opening in the inter-metal dielectric layer or interlayer dielectric (ILD) between vertically spaced metallization levels. The via opening is subsequently filled with metal to form a via electrically connecting the vertically spaced apart metal features. The via opening is typically formed using conventional lithographic and etching techniques. After the via opening is formed, the via is filled with a conductive material, such as tungsten (W), using conventional techniques, and the excess conductive material on the surface of the inter-metal dielectric layer is then typically removed by chemical mechanical planarization (CMP).
A variant of the above-described process, termed xe2x80x9cdual damascenexe2x80x9d processing, involves the formation of an opening having a lower contact or via opening section which communicates with an upper trench section. The opening is then filled with a conductive material to simultaneously form a contact or via in contact with a conductive line. Excess conductive material on the surface of the inter-metal dielectric layer is then removed by CMP. An advantage of the dual damascene process is that the contact or via and the upper line are formed simultaneously.
High performance microprocessor applications require high speed semiconductor circuitry, and the integrated circuit speed varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases, in accordance with submicron design rules, the rejection rate due to integrated circuit speed delays significantly reduces manufacturing throughput and increases manufacturing costs.
One way to increase the circuit speed is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notably aluminum (Al) or an alloy thereof, and etching, or by damascene techniques. Al is conventionally employed because it is relatively inexpensive, exhibits low resistivity and is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the sub-micron range, step coverage problems result from the use of Al. Poor step coverage causes high current density and enhanced electromigration. Moreover, low dielectric constant polyamide materials, when employed as inter-metal dielectric layers, create moisture/bias reliability problems when in contact with Al, and these problems have decreased the reliability of interconnections formed between various metallization levels.
One approach to improved interconnection paths in vias involves the use of completely filled plugs of a metal, such as W. Accordingly, many current semiconductor devices utilizing VLSI (very large scale integration) technology employ Al for the metallization level and W plugs for interconnections between the different metallization levels. The use of W, however, is attendant with several disadvantages. For example, most W processes are complex and expensive. Furthermore, W has a high resistivity, which decreases circuit speed. Moreover, Joule heating may enhance electromigration of adjacent Al wiring. Still a further problem is that W plugs are susceptible to void formation, and the interface with the metallization level usually results in high contact resistance.
Another attempted solution for the Al plug interconnect problem involves depositing Al using chemical vapor deposition (CVD) or physical vapor deposition (PVD) at elevated temperatures. The use of CVD for depositing Al is expensive, and hot PVD Al deposition requires very high process temperatures incompatible with manufacturing integrated circuitry.
Copper (Cu) and Cu-based alloys are particularly attractive for use in VLSI and ULSI semiconductor devices, which require multi-level metallization levels. Cu and Cu-based alloy metallization systems have very low resistivities, which are significantly lower than W and even lower than those of previously preferred systems utilizing Al and its alloys. Additionally, Cu has a higher resistance to electromigration. Furthermore, Cu and its alloys enjoy a considerable cost advantage over a number of other conductive materials, notably silver (Ag) and gold (Au). Also, in contrast to Al and refractory-type metals (e.g., titanium (Ti), tantalum (Ta) and W), Cu and its alloys can be readily deposited at low temperatures formed by well-known xe2x80x9cwetxe2x80x9d plating techniques, such as electroless and electroplating techniques, at deposition rates fully compatible with the requirements of manufacturing throughput.
Another technique to increase the circuit speed is to reduce the capacitance of the inter-metal dielectric layers. Dielectric materials such as silicon oxide (SiO2) have been commonly used to electrically separate and isolate or insulate conductive elements of the integrated circuit from one another. However, as the spacing between these conductive elements in the integrated circuit structure has become smaller, the capacitance between such conductive elements because of the dielectric being formed from silicon oxide is more of a concern. This capacitance negatively affects the overall performance of the integrated circuit because of increased power consumption, reduced speed of the circuitry, and cross-coupling between adjacent conductive elements.
A response to the problem of capacitance between adjacent conductive elements caused by use of silicon oxide dielectrics has led to the use of other dielectric materials, commonly known as low-k dielectrics. Whereas silicon oxide has a dielectric constant of approximately 4.0, many low-k dielectrics have dielectric constants less than 3.5. Examples of low-k dielectric materials include organic or polymeric materials. Another example is porous, low density materials in which a significant fraction of the bulk volume contains air, which has a dielectric constant of approximately 1. The properties of these porous materials are proportional to their porosity. For example, at a porosity of about 80%, the dielectric constant of a porous silica film, i.e. porous SiO2, is approximately 1.5. Still another example of a low-k dielectric material is carbon doped silicon oxide wherein at least a portion of the oxygen atoms bonded to the silicon atoms are replaced by one or more organic groups such as, for example, an alkyl group such as a methyl (CH3xe2x80x94) group.
A problem associated with the use of many low-k dielectric materials is that these materials can be damaged by exposure to oxidizing or xe2x80x9cashingxe2x80x9d systems, which remove a resist mask used to form openings, such as vias, in the low-k dielectric material. This damage can cause the surface of the low-k dielectric material to become a water absorption site, if and when the damaged surface is exposed to moisture. Subsequent processing, such as annealing, can result in water vapor formation, which can interfere with subsequent filling with a conductive material of a via/opening or a damascene trench formed in the dielectric layer. For this reason, the upper surface of the low-k dielectric material is typically protected from damage during removal of the resist mask by a capping layer, such as silicon oxide, disposed over the upper surface.
A number of different variations of a damascene process using low-k dielectrics have been employed during semiconductor manufacturing. FIGS. 1A-1L depict a dual damascene process for forming vias and a second metallization level over a first metallization level, according to conventional techniques.
In FIG. 1A, a first etch stop layer 12 is deposited over a first metallization level 10. The first etch stop layer 12 acts as a passivation layer that protects the first metallization level 10 from oxidation and contamination and prevents diffusion of material from the first metallization level 10 into a subsequently formed dielectric layer. The first etch stop layer 12 also acts as an etch stop during subsequent etching of the dielectric layer. A typical material used as an etch stop is silicon nitride, and approximately 500 Angstroms of silicon nitride is typically deposited over the metallization level 10 to form the first etch stop layer 12. An illustrative process used for depositing silicon nitride is Plasma-Enhanced Chemical Vapor Deposition (PECVD).
In FIG. 1B, a first low-k dielectric layer 14 is deposited over first etch stop layer 12. The majority of low-k dielectric materials used for a dielectric layer are based on organic or inorganic polymers. The liquid dielectric material is typically spun onto the surface under ambient conditions to a desired depth. This is typically followed by a heat treatment to evaporate solvents present within the liquid dielectric material and to cure the film to form the first low-k dielectric layer 14.
In FIG. 1C, a second etch stop layer 40 is deposited over the first low-k dielectric layer 14. The second etch stop layer 40 acts as an etch stop during etching of a dielectric layer subsequently formed over the second etch stop layer 40. As with the first etch stop layer 12, a material typically used as an etch stop is silicon nitride, and approximately 500 Angstroms of silicon nitride are typically deposited over the first low-k dielectric layer 14 to form the second etch stop layer 40. An illustrative process used for depositing silicon nitride is PECVD. A via pattern 41 is etched into the second etch stop layer 40 using conventional photolithography and appropriate anisotropic dry etching techniques, such as an CF4 or CHF3 etch, often with an inert gas, such as argon (Ar), and an oxidizer, such as O2, added. These steps are not depicted in FIG. 1C and only the resulting via pattern 41 is depicted therein. The photoresist used in the via patterning is removed by an oxygen plasma, for example.
In FIG. 1D, a second low-k dielectric layer 42 is deposited over the second etch stop layer 40. After formation of the second low-k dielectric layer 42, a capping layer 13 can be formed over the second low-k dielectric layer 42. The function of the capping layer 13 is to protect the second low-k dielectric layer 42 from the process that removes a subsequently formed resist layer. The capping layer 13 can also be used as a mechanical polishing stop to prevent damage to the second low-k dielectric layer 42 during subsequent polishing away of conductive material that is deposited over the second low-k dielectric layer 42 and in a subsequently formed via and trench. Examples of materials used as a capping layer 13 include silicon oxide and silicon nitride.
In FIG. 1E, the trenches are formed in the capping layer 13 using conventional lithographic and etch techniques. The lithographic process involves depositing a resist 44 over the capping layer 13 and exposing and developing the resist 44 to form the desired pattern of the trench. The first etch, which is an anistropic reactive ion plasma dry etch, removes the exposed portions of capping layer 13.
In FIG. 1F, a second etch, which preferentially etches the material of the first dielectric layer 14 and second dielectric layer 42, anisotropically removes the dielectric material until the first etch stop layer 12 is reached. In this way, a trench 50 and via 51 are formed in the same etching operation. The second etch is typically an anisotropic etch, such as a reactive ion plasma dry etch, that removes only the exposed portions of the first low-k dielectric layer 14 directly below the opening in the second etch stop layer 40 and the exposed portions of the low-k dielectric materials. By using an anisotropic etch, the via 51 and the trench 50 can be formed with substantially perpendicular sidewalls.
In many cases, the low-k etch chemistry etches the photoresist at approximately the same rate as the low-k dielectric. The thickness of the trench photoresist may then be selected to be completely consumed by the end of the etch operation, to eliminate the need for photoresist stripping. Another etch, which is highly selective to the material of the first etch stop layer 12, then removes the portion of the etch stop layer 12 underlying via 51 until the etchant reaches the first metallization level 10, as depicted in FIG. 1G. This etch is also typically a dry anisotropic etch chemistry designed not to attack any other layers in order to expose a portion of the metallization.
In FIG. 1H, an adhesion/barrier material, such as tantalum, titanium, tungsten, tantalum nitride, or titanium nitride, is deposited. The combination of the adhesion and barrier material is collectively referred to as a diffusion barrier layer 20. The diffusion barrier layer 20 acts to prevent diffusion into the first and second dielectric layers 14, 42 of the conductive material subsequently deposited into the via 51 and trench 50.
In FIG. 1I, a layer 22 of a conductive material, for example, a Cu or Cu-based alloy, is deposited in the via 51 and trench 50 and over the capping layer 13. A typical process initially involves depositing a xe2x80x9cseedxe2x80x9d layer on the barrier layer 20 subsequently followed by conventional plating techniques, e.g., electroless or electroplating techniques, to fill the via 51 and trench 50. So as to ensure complete filling of the via 51 and trench 50, the Cu-containing conductive layer 22 is deposited as a blanket (or xe2x80x9coverburdenxe2x80x9d) layer 24 so as to overfill the trench 50 and via 51 and cover the upper surface of the capping layer 13.
In FIG. 1J, the entire excess thickness of the metal overburden layer 24 over the upper surface of the capping layer 13 is removed using a CMP process. A typical CMP process utilizes an alumina (Al2O3)-based slurry, which leaves a conductive plug in the via 51 and a second metallization level in the trench 50. The second metallization level has an exposed upper surface which is substantially co-planar with the upper surface of the capping layer 13.
One problem associated with above-identified processes is the limited choices of material for the middle etch stop layer, etch stop layer 40 in the above example. A commonly used material as an etch stop is silicon nitride, which has a dielectric constant of about 7.0. However, the use of a thick etch stop layer of silicon nitride with a low-k dielectric layer partially negates the benefits obtained by use of a low-k dielectric material because of the increased combined capacitance of the etch stop layer and dielectric layer. Accordingly, a need exists for an improved method of forming copper plugs and copper metallization with low-k dielectric layers yielding an improved combined dielectric constant and corresponding decreased combined capacitance.
This and other needs are met by embodiments of the present invention which provide, in one aspect, a method of manufacturing a low-k semiconductor structure including the steps of forming a low-k dielectric layer, forming a sacrificial etch stop layer adjacent the low-k dielectric layer, and applying energy to the sacrificial etch stop layer to diffuse a component of the sacrificial etch stop layer into the adjacent low-k dielectric layer. This diffusion of the component lowers the dielectric constant of the adjacent low-k dielectric layer.
In another aspect, the invention includes a method of manufacturing a low-k semiconductor device including the steps of forming a metallization layer, forming an etch stop layer on the metallization layer, forming a first low-k dielectric layer on the etch stop layer, forming a sacrificial carbon-bearing middle stop layer on the first low-k dielectric layer, and forming a second low-k dielectric layer on the sacrificial carbon-bearing middle stop layer. Energy is applied to the sacrificial carbon-bearing middle stop layer to diffuse carbon from the sacrificial carbon-bearing middle stop layer to at least one of the first and second low-k dielectric layers, wherein the diffusion of carbon into the first or second low-k dielectric layer lowers the dielectric constant of the corresponding low-k dielectric layer.
In other aspects, the invention includes a low-k semiconductor device including a low-k dielectric layer comprising a low-k material and a middle stop layer comprising a diffusible component disposed adjacent the low-k dielectric layer, wherein the low-k material comprises bonds formed with the diffusible component. In one aspect of this device, the middle stop layer comprises amorphous carbon, the diffusible component comprises carbon, and low-k material bonds formed with the diffusible component are Sixe2x80x94C bonds.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.